- U.S. Patent 6,922,138: Vehicle Specific Messaging Apparatus and Method
- U.S. Patent 6,981,110: Hardware Enforced Virtual Sequentiality
- U.S. Patent 7,035,998: Clustering Stream and/or Instruction Queues for Multi-Streaming Processors
- U.S. Patent 7,042,887: Method and Apparatus for Non-Speculative Pre-Fetch Operations in Data Packet Processing
- U.S. Patent 7,058,064: Queueing System for Processors in Packet Routing Operations
- U.S. Patent 7,065,096: Method for Allocating Memory Space for Limited Packet Head and/or Tail Growth
- U.S. Patent 7,107,402: Packet Processor Memory Interface
- U.S. Patent 7,139,901: Extended Instruction Set for Packet Processing Applications
- U.S. Patent 7,155,516: Method and Apparatus for Overflowing Data Packets to a Software-Controlled Memory When They Do Not Fit Into a Hardware-Controlled Memory
- U.S. Patent 7,165,257: Context Selection and Activation Mechanism for Activating One of a Group of Inactive Contexts in a Processor Core for Servicing Interrupts
- U.S. Patent 7,197,043: Method for Allocating Memory Space for Limited Packet Head and/or Tail Growth
- U.S. Patent 7,257,814: Method and Apparatus for Implementing Atomicity of Memory Operations in Dynamic Multi-Streaming Processors
- U.S. Patent 7,280,548: Method and Apparatus for Non-speculative Pre-fetch Operation in Data Packet Processing
- U.S. Patent 7,319,379: Profile-Based Messaging Apparatus and Method
- U.S. Patent 7,346,710: Apparatus for Input/Output Expansion Without Additional Control Line Wherein First and Second Signals Transition Directly to a Different State When Necessary to Perform Input/Output
- U.S. Patent 7,360,217: Multi-Threaded Packet Processing Engine for Stateful Packet Processing
- U.S. Patent 7,441,088: Packet Processor Memory Conflict Prediction
- U.S. Patent 7,444,481: Packet Processor Memory Interface With Memory Conflict Value Checking
- U.S. Patent 7,475,200: Packet Processor Memory Interface With Write Dependency List
- U.S. Patent 7,475,201: Packet Processor Memory Interface With Conditional Delayed Restart
- U.S. Patent 7,478,209: Packet Processor Memory Interface With Conflict Detection And Checkpoint Repair
- U.S. Patent 7,482,910: Apparatus, System, and Computer Program Product for Presenting Unsolicited Information to a Vehicle or Individual
- U.S. Patent 7,487,304: Packet Processor Memory Interface With Active Packet List
- U.S. Patent 7,496,721: Packet Processor Memory Interface With Late Order Binding
- U.S. Patent 7,506,104: Packet Processor Memory Interface With Speculative Memory Reads
- U.S. Patent 7,529,907: Method and Apparatus for Improved Computer Load and Store Operations
- U.S. Patent 7,551,626: Queueing System for Processors in Packet Routing Operations
- U.S. Patent 7,606,942: Method for Input Output Expansion in an Embedded System Utilizing Controlled Transitions of First and Second Signals
- U.S. Patent 7,650,605: Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
- U.S. Patent 7,668,954: Unique Identifier Validation